This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced reconfigurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned*
Aqib Perwaiz, Hamid M Kamboh, Shoab A Khan. (2010) FPGA Fabric Specific Optimization for RTL Design, Pakistan Journal of Engineering and Applied Sciences, Volume 6, Issue 1.